Wiring substrate and method for manufacturing wiring substrate

ABSTRACT

A method for manufacturing a wiring substrate includes forming a second resin insulating layer on a first resin insulating layer such that the second resin insulating layer is in contact with a surface of the first resin insulating layer, irradiating laser upon the second resin insulating layer such that a recess penetrating through the second resin insulating layer and exposing the first resin insulating layer is formed, and forming a conductor layer including conductor material filled in the recess formed through the second resin insulating layer such that the conductor layer is embedded in the second resin insulating layer. The second resin insulating layer are formed on the surface of the first resin insulating layer such that the first resin insulating layer and the second resin insulating layer have different processability with respect to the laser.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is based upon and claims the benefit of priorityto Japanese Patent Application No. 2021-166373, filed Oct. 8, 2021, theentire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION Field of the Invention

The present invention relates to a wiring substrate and a method formanufacturing the wiring substrate.

Description of Background Art

International Publication No. 2010/004841 describes a print wiringsubstrate that includes a first insulating layer, a second insulatinglayer formed on the first insulating layer, a recess formed in thesecond insulating layer, and a second conductor circuit formed byfilling the recess in the second insulating layer. The entire contentsof this publication are incorporated herein by reference.

SUMMARY OF THE INVENTION

According to one aspect, a method for manufacturing a wiring substrateincludes forming a second resin insulating layer on a first resininsulating layer such that the second resin insulating layer is incontact with a surface of the first resin insulating layer, irradiatinglaser upon the second resin insulating layer such that a recesspenetrating through the second resin insulating layer and exposing thefirst resin insulating layer is formed, and forming a conductor layerincluding conductor material filled in the recess formed through thesecond resin insulating layer such that the conductor layer is embeddedin the second resin insulating layer. The second resin insulating layerare formed on the surface of the first resin insulating layer such thatthe first resin insulating layer and the second resin insulating layerhave different processability with respect to the laser.

According to another aspect, a wiring substrate includes a first resininsulating layer, a second resin insulating layer formed on the firstresin insulating layer such that the second resin insulating layer is incontact with a surface of the first resin insulating layer, and aconductor layer including conductor material and formed in the secondresin insulating layer such that the conductor layer is embedded in thesecond resin insulating layer. The second resin insulating layer has arecess penetrating through the second resin insulating layer andexposing the first resin insulating layer at a bottom of the recess suchthat the recess is filled with the conductor material of the conductorlayer.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete appreciation of the invention and many of the attendantadvantages thereof will be readily obtained as the same becomes betterunderstood by reference to the following detailed description whenconsidered in connection with the accompanying drawings, wherein:

FIG. 1 is a cross-sectional view illustrating an example of a wiringsubstrate according to an embodiment of the present invention;

FIG. 2 is a partial enlarged view of FIG. 1 , which is an example of thewiring substrate according to the embodiment of the present invention;

FIG. 3A is a cross-sectional view illustrating a method formanufacturing a wiring substrate according to an embodiment of thepresent invention;

FIG. 3B is a cross-sectional view illustrating a method formanufacturing a wiring substrate according to an embodiment of thepresent invention;

FIG. 3C is a cross-sectional view illustrating a method formanufacturing a wiring substrate according to an embodiment of thepresent invention;

FIG. 3D is a cross-sectional view illustrating a method formanufacturing a wiring substrate according to an embodiment of thepresent invention;

FIG. 3E is a partial enlarged view of a cross-sectional viewillustrating a method for manufacturing a wiring substrate according toan embodiment of the present invention;

FIG. 3F is a partial enlarged view of a cross-sectional viewillustrating a method for manufacturing a wiring substrate according toan embodiment of the present invention;

FIG. 3G is a partial enlarged view of a cross-sectional viewillustrating a method for manufacturing a wiring substrate according toan embodiment of the present invention;

FIG. 3H is a cross-sectional view illustrating a method formanufacturing a wiring substrate according to an embodiment of thepresent invention;

FIG. 3I is a cross-sectional view illustrating a method formanufacturing a wiring substrate according to an embodiment of thepresent invention; and

FIG. 3J is a cross-sectional view illustrating a method formanufacturing a wiring substrate according to an embodiment of thepresent invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Embodiments will now be described with reference to the accompanyingdrawings, wherein like reference numerals designate corresponding oridentical elements throughout the various drawings.

A wiring substrate according to an embodiment of the present inventionis described with reference to the drawings. The drawings to bereferenced below are drawn such that features according to embodimentsof the present invention are easily understood, without intending toshow exact proportions of structural elements. FIG. 1 illustrates across-sectional view of a wiring substrate 1 as an example of astructure that a wiring substrate according to an embodiment of thepresent invention has.

As illustrated in FIG. 1 , the wiring substrate 1 includes a coresubstrate 100 that includes an insulating layer (core insulating layer)101 and conductor layers (core conductor layers) 102 formed on bothsides of the core insulating layer 101. On each of both sides of thecore substrate 100, insulating layers and conductor layers arelaminated. In the illustrated example, a first build-up part 10 in whichinsulating layers (11, 111, 112) and conductor layers (12, 121) arelaminated is formed on a surface (F1) on one side of the core substrate100. Further, a second build-up part 20 in which insulating layers 21and conductor layers 22 are laminated is formed on a surface (F2) on theother side of the core substrate 100.

In the description of the wiring substrate of the present embodiment, aside farther from the core insulating layer 101 is referred to as“upper,” “upper side,” “outer side,” or “outer,” and a side closer tothe core insulating layer 101 is referred to as “lower,” “lower side,”“inner side,” or “inner.” Further, for the insulating layers and theconductor layers, a surface facing the opposite side with respect to thecore substrate 100 is also referred to as an “upper surface,” and asurface facing the core substrate 100 side is also referred to as a“lower surface.” Therefore, for example, in the description of thestructural elements of the first build-up part 10 and the secondbuild-up part 20, a side farther from the core substrate 100 is alsoreferred to as an “upper side,” “upper-layer side,” or “outer side,” orsimply “upper” or “outer,” and a side closer to the core substrate 100is also referred to as a “lower side,” “lower-layer side,” or “innerside,” or simply “lower” or “inner.”

For example, an insulating layer 110, which is a solder resist layer, isformed on the first build-up part 10. For example, an insulating layer210, which is a solder resist layer, is formed on the second build-uppart 20. Openings (110 a) are formed in the insulating layer 110, andconductor pads (12 p) of the outermost conductor layer 12 in the firstbuild-up part 10 are exposed from the openings (110 a). Openings (210 a)are formed in the insulating layer 210, and conductor pads (22 p) of theoutermost conductor layer 22 in the second build-up part 20 are exposedfrom the openings (210 a).

An outermost surface of the wiring substrate 1 formed of exposedsurfaces of the conductor layer 12 (conductor pads (12 p)) and theinsulating layer 110 is referred to as a first surface (FA). Anoutermost surface of the wiring substrate 1 formed of exposed surfacesof the insulating layer 210 and the conductor layer 22 (conductor pads(22 p)) is referred to as a second surface (FB). That is, the wiringsubstrate 1 has the first surface (FA) and the second surface (FB) onthe opposite side with respect to the first surface (FA) as two surfacesthat extend in a direction orthogonal to a thickness direction of thewiring substrate 1.

In the insulating layer 101 of the core substrate 100, through-holeconductors 103 are formed connecting the conductor layer 102 that formsthe surface (F1) on the one side of the core substrate 100 and theconductor layer 102 that forms the surface (F2) on the other side of thecore substrate 100. In the insulating layers (11, 111, 21), viaconductors (13, 23) connecting the conductor layers sandwiching theinsulating layers (11, 111, 21) are formed.

The conductor layer 121 in the first build-up part 10 of the illustratedwiring substrate 1 has a structure different from the other conductorlayers (102, 12, 22) forming the wiring substrate 1. Specifically, theconductor layers (102, 12, 22) are in a form in which side surfaces andupper surfaces of conductor patterns are covered by the insulatinglayers (11, 111, 110, 21, 210) covering upper sides of the conductorlayers (102, 12, 22). The conductor layer 121 has a structure differentfrom these conductor layers (102, 12, 22). An upper surface of theconductor layer 121 is in contact with the insulating layer 11 and aside surface of the conductor layer 121 is in contact with theinsulating layer 112. In other words, the conductor layer 121 is in aform of being embedded in the insulating layer 112. Further, theconductor layer 121 penetrates the insulating layer 112 in the thicknessdirection, and a lower surface of the conductor layer 121 is in contactwith the insulating layer 111. That is, the conductor layer 121 is in aform of penetrating the insulating layer 112 in the thickness direction,and has a thickness substantially equal to that of the insulating layer112. In the present specification, a conductor layer (such as theconductor layer 121) that is in a form of being embedded in aninsulating layer and penetrates the insulating layer and has a thicknesssubstantially equal to that of the insulating layer is referred to as a“penetrating conductor layer” for the sake of description.

The conductor layers (102, 12, 121, 22), the via conductors (13, 23),and the through-hole conductors 103 may be formed using a metal such ascopper or nickel, and, for example, may be formed of a metal foil suchas a copper foil and/or a metal film formed by plating or sputtering orthe like. The conductor layers (102, 12, 121, 22), the via conductors(13, 23), and the through-hole conductors 103 are illustrated in FIG. 1as having a single-layer structure, but may have a multilayer structurethat includes two or more metal layers. For example, each of theconductor layers 102 that are respectively formed on the surfaces ofinsulating layer 101 has a three-layer structure including a metal foil,an electroless plating film, and an electrolytic plating film. Further,each of the conductor layers (12, 121, 22), the via conductors (13, 23),and the through-hole conductors 103 has, for example, a two-layerstructure including an electroless plating film and an electrolyticplating film.

Each of the conductor layers (102, 12, 121, 22) of the wiring substrate1 is patterned to have predetermined conductor patterns. In particular,in the illustrated example, as will be described later, the conductorlayer 121 is formed to have relatively fine patterns by filling recessespenetrating the insulating layer 112 formed on an outer side of theinsulating layer 111. Specifically, the conductor layer 121 has wirings(FW) as relatively fine patterns. Further, the conductor layer 121 alsohas land parts (L) as connecting parts to the via conductors 13 thatconnect to an outer side of the conductor layer 121.

In the following description, the insulating layer 111 is also referredto as the first resin insulating layer 111, the insulating layer 112 isalso referred to as the second resin insulating layer 112, and theconductor layer 121 is also referred to as the first conductor layer121. The wiring substrate of the present embodiment includes at leastthe first resin insulating layer 111, the second resin insulating layer112 that is laminated on an upper surface of the first resin insulatinglayer 111, and the first conductor layer 121 that penetrates the secondresin insulating layer 112 and has a thickness substantially equal tothat of the second resin insulating layer 112.

The outermost conductor layer 12 of the first build-up part 10 is formedto have patterns including the conductor pads (12 p). The conductor pads(12 p) are formed such that a component (not illustrated in thedrawings) to be mounted on the wiring substrate 1 when the wiringsubstrate 1 is used can be placed. That is, the conductor pads (12 p)are component mounting pads to be used as connecting parts when anexternal component is mounted on the wiring substrate 1, and the firstsurface (FA) of the wiring substrate 1 is a component mounting surfaceon which a component can be mounted. Electrodes of an electroniccomponent can be electrically and mechanically connected to thecomponent mounting pads (conductor pads) (12 p), for example, via abonding material (not illustrated in the drawings) such as solder.Examples of components that are mounted on the wiring substrate 1include electronic components such as active components such assemiconductor integrated circuit devices and transistors.

The second surface (FB), which is a surface on the opposite side withrespect to the first surface (FA) of the wiring substrate 1 in theexample of FIG. 1 , is a connection surface that is to be connected toan external wiring substrate, for example, an external element such as amotherboard of an electrical device when the wiring substrate 1 itselfis mounted on the external element. Further, similarly to the firstsurface (FA), the second surface (FB) may be a component mountingsurface on which an electronic component such as a semiconductorintegrated circuit device is mounted. Without being limited to these,the conductor pads (22 p) forming the second surface (FB) can beconnected to a substrate, an electrical component, a mechanism element,or the like.

Each of the insulating layers (101, 11, 111, 112, 21) may be formed, forexample, using an insulating resin such as an epoxy resin, abismaleimide triazine resin (BT resin) or a phenol resin. For example,each of the insulating layers (110, 210), which are solder resistlayers, may be formed using, for example, a photosensitive epoxy resinor polyimide resin, or the like. Each of the insulating layers (101, 11,111, 112, 21, 110, 210) may contain an inorganic filler such as silica,or alumina. Each of the insulating layers (101, 11, 111, 21) may alsocontain a reinforcing material (core material) such as a glass fiber.

As will be described in detail later, the second resin insulating layer112 in which the first conductor layer 121 is embedded, and the firstresin insulating layer 111 may have different filler volume contentrates. Specifically, the filler volume content rate of the second resininsulating layer 112 may be smaller than the filler volume content rateof the first resin insulating layer 111. Furthermore, an averageparticle size of the filler contained in the second resin insulatinglayer 112 may be smaller than an average particle size of the fillercontained in the first resin insulating layer 111. When the fillerscontained in the first resin insulating layer 111 and the second resininsulating layer 112 have the above relations, as will be describedlater regarding a method for manufacturing a wiring substrate, it may bepossible that the formation of the first conductor layer 121 in a formof a penetrating conductor layer is more precisely performed.

Further, the fillers contained in the first resin insulating layer 111and the second resin insulating layer 112 have the above relations, itmay be possible that undesirable short circuit or insulation or the likein the wirings (FW) or the like of the first conductor layer 121 issuppressed. When the recesses in the second resin insulating layer 112are formed in a process of forming the first conductor layer 121, it maybe possible that filler particles contained in the second resininsulating layer 112 are exposed in the recesses. It may be possiblethat the filler particles exposed in the recesses protrude to innersides of the recesses, and as a result, cause a local increase inimpedance in the wiring patterns of the first conductor layer 121.Further, it may also be possible that the filler particles exposed inthe recesses fall off during a desmear treatment in the recesses, andfiller loopholes are formed in the second resin insulating layer 112. Itmay also be possible that the filler loopholes are filled with aconductor and distances between adjacent wirings are reduced and a riskof a short circuit is increased.

In particular, the relatively fine wirings (FW) in the first conductorlayer 121 are likely to be affected by such filler particles, and thiscan lead to poor transmission of signals carried by the wirings (FW).The larger the number of filler particles exposed in the recesses, andthe larger the relative sizes of the filler particles exposed in therecesses, the more pronounced this problem can become. Therefore, whenthe volume content rate and the average particle size of the filler inthe second resin insulating layer 112 are smaller than the volumecontent rate and the average particle size of the filler in the firstresin insulating layer 111, it may be possible that occurrence of theproblem is suppressed.

Next, with reference to FIG. 2 , the structures of the first conductorlayer 121 in a form of a penetrating conductor layer, the second resininsulating layer 112 penetrated by the first conductor layer 121, andthe first resin insulating layer 111 as an insulating layer directlybelow the second resin insulating layer 112 are described in detail.FIG. 2 is an enlarged view of a region that is indicated by a referencenumeral symbol “II” and is surrounded by a one-dot chain line in thecross-sectional view of FIG. 1 , and includes the first resin insulatinglayer 111, the second resin insulating layer 112, and the firstconductor layer 121. In the example illustrated in FIG. 2 , each of theconductor layer 12 and the via conductors 13 has a two-layer structureincluding a metal film layer (electroless plating film layer) (12 a) andan electrolytic plating film layer (12 b), and the first conductor layer121 is similarly formed of a metal film layer (12 a) and an electrolyticplating film layer (12 b).

The first conductor layer 121 penetrates the second resin insulatinglayer 112 and is in contact with both the insulating layer 11 and thefirst resin insulating layer 111 which are respectively in contact withan upper side and a lower side of the second resin insulating layer 112.The first conductor layer 121 has a two-layer structure including themetal film layer (12 a), which covers inner surfaces of recesses (op 1,op 2) formed in the second resin insulating layer 112, and theelectrolytic plating film layer (12 b), which fills an inner side of themetal film layer (12 a). Specifically, as will be described later in thedescription of the method for manufacturing a wiring substrate, therecesses (op 1, op 2) are formed by irradiating laser from an upper sideof the second resin insulating layer 112. The recesses (op 1, op 2)penetrating the second resin insulating layer 112 in the thicknessdirection are formed in the second resin insulating layer 112 byremoving a resin component by ablation by laser irradiation. Therecesses (op 1) correspond to the wirings (FW) that the first conductorlayer 121 have, and the recesses (op 2) correspond to the land parts(L).

Specifically, as will be described later regarding the method formanufacturing the wiring substrate, the second resin insulating layer112 and the first resin insulating layer 111 are different from eachother in processability (machinability) with respect to laserirradiation, and when laser penetrates the second resin insulating layer112 and reaches the upper surface of the first resin insulating layer111, the laser processing is substantially stopped. Therefore, a depth(D) of the recesses (op 1, op 2) is substantially the same as athickness (T) of the second resin insulating layer 112. Specifically,the thickness (T) of the second resin insulating layer 112 is about 10µm - 20 µm, and the first conductor layer 121 is formed to havesubstantially the same thickness. The laser processability of each ofthe resin insulating layers (the second resin insulating layer 112 andthe first resin insulating layer 111) is controlled by adjusting anabsorbance coefficient with respect to the laser or a content rate ofthe filler contained or the like. The depth (D) of the recesses (op 1,op 2) may be larger than the thickness (T) of the second resininsulating layer 112, and bottoms of the recesses (op 1, op 2) may beformed protruding to the first resin insulating layer 111 side from aninterface between the first resin insulating layer 111 and the secondresin insulating layer 112.

In the cross-sectional view of FIG. 2 , the wirings (FW), which areillustrated as multiple (4 in the illustrated example) wirings extendingin parallel in a direction perpendicular to the paper (that is, from afront side to a back side of the page), are formed with relatively smallline widths and inter-line distances. For example, the wirings (FW) havea smallest line width and a smallest inter-line distance of about 2 µm -5 µm. As described above, it may be preferable, especially from a pointof view of suppressing a short circuit and insulation in the wirings(FW), that the volume content rate and average particle size of thefiller contained in the second resin insulating layer 112 are smallerthan the volume content rate and average particle size of the fillercontained in the first resin insulating layer 111.

Specifically, from a point of view of suppressing a short circuit and adisconnection of the wirings (FW) and allowing each of the first andsecond resin insulating layers (111, 112) to have a desirable laserprocessability, for example, the volume content rate of the filler inthe second resin insulating layer 112 is about 5% - 15%, and the volumecontent rate of the filler in the first resin insulating layer 111 isabout 50% - 80%. Further, the average particle size of the fillercontained in the second resin insulating layer 112 is about 0.25 µm, andthe average particle size of the filler contained in the first resininsulating layer 111 is about 0.5 µm. Further, in particular, from apoint of view of suppressing a short circuit and insulation in thewirings (FW), a maximum particle size of the filler contained in thesecond resin insulating layer 112 is preferably equal to or less than apredetermined ratio with respect to the line width and inter-linedistance of the wirings (FW). For example, the maximum particle size ofthe filler contained in the second resin insulating layer 112 is 50% orless of the line width and inter-line distance of the relatively finewirings (FW).

In the above, the wiring substrate 1 is described above as an example inwhich only one first conductor layer 121 in a form of a penetratingconductor layer is formed in the first build-up part 10. However, anynumber of penetrating conductor layers may be formed at any positionswithin a wiring substrate. For example, also in the second build-up part20, a penetrating conductor layer may be formed as a conductor layer ofthe same rank as the first conductor layer 121. The term “rank” is anumber assigned to each conductor layer when the number that increasesby 1 for each layer starting from the core substrate 100 side issequentially assigned starting from 1 to each of the multiple conductorlayers laminated in each of the first build-up part 10 and the secondbuild-up part 20. By forming in the second build-up part 20 apenetrating conductor layer with the same rank as that in the firstbuild-up part 10, it may be possible that symmetricity in the thicknessdirection of the wiring substrate is improved and warpage of the wiringsubstrate is suppressed.

With reference to FIGS. 3A - 3J, a method for manufacturing a wiringsubstrate, which is an embodiment, is described using a case where thewiring substrate 1 illustrated in FIG. 1 is manufactured as an example.First, as illustrated in FIG. 3A, the core substrate 100 is prepared. Inthe preparation of the core substrate 100, for example, a double-sidedcopper-clad laminated plate including the core insulating layer 101 isprepared. Then, the core substrate 100 is prepared by using asubtractive method or the like to form the conductor layers 102including predetermined conductor patterns on both sides of theinsulating layer 101 and form the through-hole conductors 103 in theinsulating layer 101.

Next, as illustrated in FIG. 3B, the insulating layer 11 is formed onthe surface (F1) on one side of the core substrate 100, and theconductor layer 12 is laminated on the insulating layer 11. Theinsulating layer 21 is formed on the surface (F2) on the other side ofthe core substrate 100, and the conductor layer 22 is laminated on theinsulating layer 21. For example, each of the insulating layers (11, 21)is formed by thermocompression bonding a film-like insulating resin ontothe core substrate 100. The conductor layers (12, 22) are formed using amethod for forming conductor patterns, such as a semi-additive method,at the same time as the via conductors (13, 23) filling openings (13 a,23 a) that are formed in the insulating layers (11, 21), for example,using laser.

Next, as illustrated in FIG. 3C, on the surface (F1) side of the coresubstrate 100, the first insulating layer 111 and the second insulatinglayer 112 are laminated. On the surface (F2) side, the insulating layer21 is laminated on the conductor layer 22. The first resin insulatinglayer 111 and the second resin insulating layer 112 are formed usingmaterials that are different in laser processability in forming therecesses in the second resin insulating layer 112 to be described later.The laser processability of each of the first and second resininsulating layers (111, 112) is adjusted, for example, depending on anamount of an additive (a curing accelerator and/or a curing inhibitor)and/or a volume content rate and an average particle size of fillercontained, or the like.

Next, as illustrated in FIG. 3D, for example, by laser processing,openings (vo) are formed that continuously penetrate the secondinsulating layer 112 and the first resin insulating layer 111 to exposethe conductor layer 12 at bottoms thereof. The openings (vo) are formedat positions where the via conductors 13 (see FIG. 1 ) penetrating thefirst insulating layer 111 are to be formed. For forming the openings(vo), for example, CO₂ laser with a relatively long wavelength of about10 µm may be used.

Next, as illustrated in FIG. 3E, the recesses (op 1, op 2) are formed inthe second resin insulating layer 112. Each of FIGS. 3E - 3G illustratesan enlarged view of a region corresponding to that of FIG. 2 near thefirst resin insulating layer 111, the second resin insulating layer 112,and the recesses (op 1, op 2) in a formation process of the wiringsubstrate 1.

For example, the recesses (op 1, op 2) that expose the first resininsulating layer 111 at bottoms thereof are formed by processing usingexcimer laser that has a relatively short wavelength and relativelyexcellent straightness in processing an insulating layer. The recesses(op 1, op 2) are formed according to the wiring patterns to be formed inthe first conductor layer 121, which is formed penetrating the secondresin insulating layer 112. As illustrated, the recesses (op 1)correspond to the land parts (L) and the recesses (op 2) correspond tothe wirings (FW) of the first conductor layer 121 to be formed (see FIG.1 ). Inner surfaces of the formed recesses (op 1, op 2) and openings(vo) may be subjected to a desmear treatment using a chemical solutioncontaining an oxidizing agent such as permanganate.

In the formation of the recesses (op 1, op 2), the recesses (op 1, op 2)penetrating the second resin insulating layer 112 are drilled byablation with laser such as excimer laser irradiated from an upper sideof the second resin insulating layer 112. The second resin insulatinglayer 112 is formed using a material having a relatively high laserprocessability, and the first resin insulating layer 111 is formed usinga material having a relatively low laser processability. Therefore,after the processing (drilling) with respect to the second resininsulating layer 112 by laser irradiation is completed and the firstresin insulating layer 111 is exposed at the bottoms of the recesses (op1, op 2), the first resin insulating layer 111 is substantiallydifficult to be processed by laser. For example, a certain time periodis ensured before the first resin insulating layer 111 begins to besubjected to substantial processing. By stopping laser irradiationwithin that time period, the recesses (op 1, op 2) penetrating only thesecond resin insulating layer 112 are formed. In other words, therecesses (op 1, op 2) penetrating the second resin insulating layer 112and having a depth (D) that is substantially the same as the thickness(T) of the second resin insulating layer 112 are realized by adifference in laser processability between the first resin insulatinglayer 111 and the second resin insulating layer 112. The depth (D) ofthe formed recesses (op 1, op 2) may be larger than the thickness (T) ofthe second resin insulating layer 112, and the bottoms of the recesses(op 1, op 2) may be formed protruding to the first resin insulatinglayer 111 side from the interface between the first resin insulatinglayer 111 and the second resin insulating layer 112.

The laser processability of a resin insulating layer is adjusted, forexample, depending on an absorbance coefficient with respect to awavelength of laser to be used. When the processability with respect tothe wavelength of the laser is adjusted depending on the absorbancecoefficient, the absorbance coefficient of the second resin insulatinglayer 112 is larger than the absorbance coefficient of the first resininsulating layer 111. For example, in order to make the absorbancecoefficient of the second resin insulating layer 112 and the absorbancecoefficient of the first resin insulating layer 111 different from eachother with respect to laser, an amount of an additive that is containedin each of the second resin insulating layer 112 and the first resininsulating layer 111 is adjusted. An example of the additive is a curinginhibitor, which is a pigment such as carbon black. Further, theadditive may be, for example, a curing accelerator such as imidazole,triphenylphosphine, a sulfonium salt, or the like.

Further, for example, it is also possible that a difference in laserprocessability is provided depending on compositions or structures ofresin materials forming the second resin insulating layer 112 and thefirst resin insulating layer 111. For example, the second resininsulating layer 112 may be formed of an amorphous resin (such as an ABSresin), and the first resin insulating layer 111 may be formed of acrystalline resin (such as a liquid crystal polymer (LCP)).

Further, it is also possible that a difference in laser processabilityis provided by adjusting the volume content rate of the filler that iscontained in the second resin insulating layer 112 and the first resininsulating layer 111. It may be possible that the higher the volumecontent rate of the filler, the more impeded the progress of laserprocessing in the thickness direction of the resin insulating layer.Therefore, it may be possible that the filler volume content rate of thesecond resin insulating layer 112 is relatively small, and the fillervolume content rate of the first resin insulating layer 111 isrelatively large. Further, a difference in laser processability isprovided by providing a difference in average particle size between thefillers contained in the first and second resin insulating layers (111,112). For example, by making the average particle size of the fillercontained in the first resin insulating layer 111 larger than theaverage particle size of the filler contained in the second resininsulating layer 112, it may be possible that the laser machinability ofthe second resin insulating layer 112 is made higher than that of thefirst resin insulating layer 111. The term “particle size” in thedescription of filler particles means a linear distance between two mostdistant points on an outer surface of a filler particle. In the casewhere a difference in laser processability is provided by adjusting thefiller volume content rates, when the first and second resin insulatinglayers (111, 112) are formed, for example, the second resin insulatinglayer 112 having a filler volume content rate of about 5% - 15% and thefirst resin insulating layer 111 having a filler volume content rate ofabout 50% - 80% are formed. Further, the average particle size of thefiller in the second resin insulating layer 112 is about 0.25 µm, andthe average particle size of the filler in the first resin insulatinglayer 111 is about 0.5 µm. Further, it may be possible that the maximumparticle size of the filler contained in the second resin insulatinglayer 112 to be formed is limited to 50% or less of a width of each ofthe recesses (op 1) to be formed and a width between adjacent recesses(op 1).

The formation order of the openings (vo) and the recesses (op 1, op 2)described with reference to FIGS. 3D and 3E may be arbitrarily changed.For example, the recesses (op 1, op 2) may be formed prior to theformation of the openings (vo). After the lamination of first resininsulating layer 111 and the second resin insulating layer 112illustrated in FIG. 3C and before the formation of the openings (vo) andthe recesses (op 1, op 2), a surface of the insulating layer 21 exposedon the other surface (F2) side of the core substrate 100 isappropriately protected using a mask such as a PET film.

Next, as illustrated in FIG. 3F, a conductor layer (121 p) is formedthat covers the entire upper surface of the second resin insulatinglayer 112 and fills the recesses (op 1, op 2) and the openings (vo). Forexample, first, a metal film layer (12 a) is formed by electrolessplating or sputtering or the like. The metal film layer (12 a) coversinner surfaces of the openings (vo) and the recesses (op 1, op 2) andthe entire upper surface of the second resin insulating layer 112. Next,electrolytic plating is performed using the metal film layer (12 a) as apower feeding layer, and a plating film layer (12 b) is formed. An innerside of the metal film layer (12 a) in the openings (vo) and therecesses (op 1, op 2) is filled with a conductor, and the conductorlayer (121 p) covering the entire upper surface of the second resininsulating layer 112 is formed.

Next, as illustrated in FIG. 3G, a portion of the conductor layer (121p) above the upper surface of the second resin insulating layer 112 inthe thickness direction is removed by polishing. The polishing of theconductor layer (121 p) is performed, for example, by chemicalmechanical polishing (CMP). When the polishing is completed, the uppersurface of the second resin insulating layer 112 and the upper surfaceof the first conductor layer 121 are substantially flush with eachother.

As described above, the depth (D) of the recesses (op 1, op 2) formedpenetrating the second resin insulating layer 112 is substantially equalto the thickness (T) of the second resin insulating layer 112.Therefore, the thickness of the first conductor layer 121 formed of themetal film layer (12 a) and the plating film layer (12 b) filling therecesses (op 1, op 2) is also substantially equal to the thickness (T)of the second resin insulating layer 112. That is, according to themethod for manufacturing the wiring substrate of the present embodiment,controlling a thickness of a conductor layer embedded in a resininsulating layer is realized by controlling a thickness of the resininsulating layer. A thickness of a conductor layer in a form of beingembedded in an insulating layer is precisely controlled.

Through the above processes, the wiring substrate is in a state asillustrated in FIG. 3H. The second resin insulating layer 121 is in astate of being exposed, and the formation of the first conductor layer121 in a form of a penetrating conductor layer, which is embedded in thesecond resin insulating layer 112 and includes the wirings (FW) and theland parts (L), is completed.

Next, as illustrated in FIG. 3I, on the other surface (F2) side of thecore substrate 100, the conductor layers 22 are integrally formed withthe via conductors 23.

On the surface (F1) side of the core substrate 100, using the samemethod as the formation of the insulating layer 11 and the conductorlayer 12 on the core substrate 100 described above, an insulating layer11 and a conductor layer 12 are further formed on the upper side of theconductor layer 112. The formation of the first build-up part 10 on thesurface (F1) side of the core substrate 100 is completed. On the othersurface (F2) side of the core substrate 100, one insulating layer 21 andconductor layers 22 are further alternately laminated. The formation ofthe second build-up part 20 on the other surface (F2) side is completed.The outermost conductor layer 12 of the first build-up part 10 is formedto have patterns including the conductor pads (12 p), and the outermostconductor layer 22 of the second build-up part 20 is formed to havepatterns including the conductor pads (22 p).

Next, as illustrated in FIG. 3J, for example, the insulating layers(110, 210), which are solder resist layers, are respectively formed onthe first and second build-up parts (10, 20). For example,photosensitive epoxy resin films are formed by spray coating, curtaincoating, or film pasting, and the openings (110 a, 210 a) are formed byexposure and development. The conductor pads (12 p, 22 p) are exposedfrom the openings (110 a, 210 a) of the insulating layers (110, 210). Bythe above processes, the formation of the wiring substrate 1 iscompleted. After the formation of the openings (110 a, 210 a), aprotective film (not illustrated in the drawings) may be formed on theexposed surface of each of the conductor pads (12 p, 22 p). For example,the protective film formed of Ni/Au, Ni/Pd/Au, Sn or the like may beformed by plating. An OSP film may be formed by spraying an organicmaterial.

The wiring substrate of the embodiment is not limited to those havingthe structures illustrated in the drawings and those having thestructures, shapes, and materials exemplified herein. For example, oneor more conductor layers each in a form of a penetrating conductor layerare provided among the conductor layers forming the wiring substrate.The wiring substrate of the embodiment may have the first conductorlayer in a form of a penetrating conductor layer, and the first resininsulating layer and the second resin insulating layer, and is notlimited to a form of having a core substrate. Each of the first build-uppart and the second build-up part may include any number of insulatinglayers and conductor layers. The number of insulating layers andconductor layers of the first build-up part and the number of insulatinglayers and conductor layers of the second build-up part formed on bothsides of the core substrate may be different from each other. The methodfor manufacturing the wiring substrate of the present embodiment is notlimited to the method described with reference to the drawings.Conditions, processing orders and the like of the method may beappropriately modified. Depending on a structure of an actuallymanufactured wiring substrate, some of the processes may be omitted, orother processes may be added.

International Publication No. 2010/004841 describes a print wiringsubstrate that includes a first insulating layer, a second insulatinglayer formed on the first insulating layer, a recess formed in thesecond insulating layer, and a second conductor circuit formed byfilling the recess in the second insulating layer. The recess filledwith a conductor forming the second conductor circuit is formed to havea depth less than a thickness of the second insulating layer by laserprocessing the second insulating layer.

In a method for manufacturing a printed wiring substrate described inInternational Publication No. 2010/004841, in the formation of therecess, it is necessary to stop the laser processing in the middle in athickness direction of the second insulating layer. Therefore, it isthought that it is difficult to precisely control the depth of therecess. It is thought that it is difficult to precisely form the secondconductor circuit, which is formed in the recess, to have a desiredthickness.

A method for manufacturing a wiring substrate according to an embodimentof the present invention includes: forming a first resin insulatinglayer and a second resin insulating layer in contact with an uppersurface of the first resin insulating layer; forming a recesspenetrating the second resin insulating layer and exposing the firstresin insulating layer at a bottom of the recess by irradiating laser;and forming a first conductor layer in a form of being embedded in thesecond resin insulating layer by filling the recess with a conductor.The first resin insulating layer and the second resin insulating layerare different from each other in processability with respect to thelaser.

A wiring substrate according to an embodiment of the present inventionincludes: a first resin insulating layer; a second resin insulatinglayer formed in contact with an upper surface of the first resininsulating layer; and a recess penetrating the second resin insulatinglayer and exposing the first resin insulating layer at a bottom of therecess. The recess is filled with the first conductor layer.

According to an embodiment of the present invention, a wiring substratein which a thickness of a conductor layer in a form of being embedded inan insulating layer is precisely controlled is provided.

Obviously, numerous modifications and variations of the presentinvention are possible in light of the above teachings. It is thereforeto be understood that within the scope of the appended claims, theinvention may be practiced otherwise than as specifically describedherein.

What is claimed is:
 1. A method for manufacturing a wiring substrate,comprising: forming a second resin insulating layer on a first resininsulating layer such that the second resin insulating layer is incontact with a surface of the first resin insulating layer; irradiatinglaser upon the second resin insulating layer such that a recesspenetrating through the second resin insulating layer and exposing thefirst resin insulating layer is formed; and forming a conductor layercomprising conductor material filled in the recess formed through thesecond resin insulating layer such that the conductor layer is embeddedin the second resin insulating layer, wherein the second resininsulating layer are formed on the surface of the first resin insulatinglayer such that the first resin insulating layer and the second resininsulating layer have different processability with respect to thelaser.
 2. The method for manufacturing a wiring substrate according toclaim 1, wherein the forming of the conductor layer includes filling therecess with the conductor material and controlling a thickness of theconductor layer such that the thickness of the conductor layer becomessubstantially equal to a depth of the recess and a thickness of thesecond resin insulating layer.
 3. The method for manufacturing a wiringsubstrate according to claim 1, wherein the second resin insulatinglayer is formed on the surface of the first resin insulating layer suchthat an absorbance coefficient of the second resin insulating layer withrespect to the laser is larger than an absorbance coefficient of thefirst resin insulating layer with respect to the laser.
 4. The methodfor manufacturing a wiring substrate according to claim 3, wherein thefirst resin insulating layer includes a curing accelerator such that avolume content rate of a curing accelerator in the second resininsulating layer is smaller than a volume content rate of the curingaccelerator in the first resin insulating layer.
 5. The method formanufacturing a wiring substrate according to claim 3, wherein thesecond resin insulating layer includes a curing inhibitor such that avolume content rate of the curing inhibitor in the second resininsulating layer is larger than a volume content rate of a curinginhibitor in the first resin insulating layer.
 6. The method formanufacturing a wiring substrate according to claim 5, wherein thecuring inhibitor is a pigment.
 7. The method for manufacturing a wiringsubstrate according to claim 1, wherein the second resin insulatinglayer includes an amorphous resin, and the first resin insulating layerincludes a crystalline resin.
 8. The method for manufacturing a wiringsubstrate according to claim 1, wherein the first resin insulating layerincludes an inorganic filler such that a volume content rate of theinorganic filler in the first resin insulating layer is larger than avolume content rate of an inorganic filler in the second resininsulating layer.
 9. The method for manufacturing a wiring substrateaccording to claim 8, wherein the second resin insulating layer includesthe inorganic filler such that an average particle size of the inorganicfiller in the first resin insulating layer is larger than an averageparticle size of the inorganic filler in the second resin insulatinglayer.
 10. The method for manufacturing a wiring substrate according toclaim 1, wherein the irradiating of the laser comprises irradiatingexcimer laser.
 11. The method for manufacturing a wiring substrateaccording to claim 1, wherein the forming of the conductor layerincludes filling the recess with the conductor material and reducing athickness of the conductor layer such that the thickness of theconductor layer becomes substantially equal to a depth of the recess anda thickness of the second resin insulating layer.
 12. The method formanufacturing a wiring substrate according to claim 1, wherein theforming of the conductor layer includes filling the recess with theconductor material and polishing the conductor layer such that athickness of the conductor layer becomes substantially equal to a depthof the recess and a thickness of the second resin insulating layer. 13.The method for manufacturing a wiring substrate according to claim 2,wherein the second resin insulating layer is formed on the surface ofthe first resin insulating layer such that an absorbance coefficient ofthe second resin insulating layer with respect to the laser is largerthan an absorbance coefficient of the first resin insulating layer withrespect to the laser.
 14. The method for manufacturing a wiringsubstrate according to claim 13, wherein the first resin insulatinglayer includes a curing accelerator such that a volume content rate of acuring accelerator in the second resin insulating layer is smaller thana volume content rate of the curing accelerator in the first resininsulating layer.
 15. The method for manufacturing a wiring substrateaccording to claim 13, wherein the second resin insulating layerincludes a curing inhibitor such that a volume content rate of thecuring inhibitor in the second resin insulating layer is larger than avolume content rate of a curing inhibitor in the first resin insulatinglayer.
 16. The method for manufacturing a wiring substrate according toclaim 15, wherein the curing inhibitor is a pigment.
 17. The method formanufacturing a wiring substrate according to claim 2, wherein thesecond resin insulating layer includes an amorphous resin, and the firstresin insulating layer includes a crystalline resin.
 18. A wiringsubstrate, comprising: a first resin insulating layer; a second resininsulating layer formed on the first resin insulating layer such thatthe second resin insulating layer is in contact with a surface of thefirst resin insulating layer; and a conductor layer comprising conductormaterial and formed in the second resin insulating layer such that theconductor layer is embedded in the second resin insulating layer,wherein the second resin insulating layer has a recess penetratingthrough the second resin insulating layer and exposing the first resininsulating layer at a bottom of the recess such that the recess isfilled with the conductor material of the conductor layer.
 19. Thewiring substrate according to claim 18, wherein the conductor layer isformed such that a thickness of the conductor layer is substantiallyequal to a thickness of the second resin insulating layer.
 20. Thewiring substrate according to claim 18, wherein the second resininsulating layer is formed such that a volume content rate of aninorganic filler in the second resin insulating layer is smaller than avolume content rate of an inorganic filler in the first resin insulatinglayer.